The present invention relates to a semiconductor integrated circuit, and more particularly to a delay locked loop (DLL) included in a semiconductor memory device.
In a system including semiconductor devices, a semiconductor memory device serves for storing data or information. When a data processor such as a CPU requests for information, the semiconductor memory device outputs data in response to an address inputted from the data processor or any other device requesting the data, or stores data, provided by a data processor, in specific internal locations corresponding to an address.
As operation speed of the system becomes faster as semiconductor integrated circuits are being advanced, a semiconductor memory device outputs or stores data at a higher operation speed. To input and output data at high speed, a synchronous memory device receives an system clock and inputs and outputs data in synchronization with the inputted system clock. To overcome limitations of prior synchronous memory devices, a double data rate (DDR) synchronous memory device, which inputs or outputs data at rising and falling edges of the system clock, is being developed.
Here, the DDR synchronous memory device processes two data within one cycle of the system clock by inputting and outputting data at each of the rising and the falling edges of the system clock. In operation, timings of outputting data from the DDR synchronous memory device are synchronized with the rising or the falling edge of the system clock. Here, a data output circuit of the DDR synchronous memory device outputs data in synchronization with the rising and the falling edges of the system clock.
However, the system clock inputted to a memory device is delayed in being transferred to the data output circuit because the system clock is delayed by a clock input buffer, a transmission line, and etc. included in the memory device. Thus, if the data output circuit outputs data in synchronization with the delayed system clock, data that is out of sync with the rising and falling edges of the system clock is actually delivered into an external device receiving data outputted from the memory device.
To the above-mentioned feature, a semiconductor memory device includes a delay locked loop used for clock recovery (i.e., to preventing the system clock from being delayed). The delay locked loop is a circuit for compensating a delay time of the system block in delivering the system clock to the data output circuit from the time of being inputted to the semiconductor memory device. The delay locked loop recognizes a delay time through a clock input buffer, a transmission line, and etc. included in the semiconductor memory device, recovers the system clock based on the delay time, and outputs the recovered system clock to the data output circuit. Here, using the delay locked loop, a delay time of a system clock inputted to the semiconductor memory device is controlled and delivered to the data output circuit. Thus, the data output circuit outputs data in synchronization with the recovered system clock, and an external circuit recognizes that outputted data is synchronized with a system clock.
In operation, a delay locked clock outputted from a delay locked loop is delivered to an output buffer one cycle earlier than the timing of outputting data. The output buffer synchronizes data with the delivered clock to output data to an external device. This means that data is outputted earlier than a system clock by a delay time of internal circuits. Through this operation, outside of the semiconductor memory device, data is accurately outputted in synchronization with each of rising and falling edges of the system clock inputted to the semiconductor memory device. The delay locked loop is a circuit configured to determine how much earlier than a system clock data is outputted to compensate for a delay time of the system clock inside the semiconductor memory device.
Thus, the delay locked loop includes a delay unit configured to delay inputted clock signal. However, since the delay unit included in the delay locked loop has a maximum delay value, a delay locking operation may not be performed properly if the delay unit is to delay the inputted clock by a delay greater than the maximum value. This issue can arise in a case that, while an inputted clock has a long cycle period, the maximum delay value of the delay unit is not increased.